Flash Storage Solutions for Embedded Designs

High Reliability Flash SSDs, Cards and Modules for Industrial Applications


Consumer product innovation has always been driven by an insatiable need to create smaller, lighter, faster and cheaper designs. This was not the case with Industrial and Embedded applications where product reliability and continuation of supply have been the drivers in component selection. However, the popularity and universal acceptance of consumer devices has also driven the embedded designs toward integration of consumer standards.

Embedded-SD-Card

Fortasa Industrial SD Card

The same could be said of the progression of Flash card standards in the embedded space. CompactFlash card was a universally accepted storage device in the embedded designs. As the consumer industry migrated rapidly from CompactFlash card to SD card and microSD form factors, the embedded designers have also migrated the new designs t use the now ubiquitous SD card standard.

Embedded application require the storage component to have very high degree of robustness, withstand environmental impact and operate reliably for the lifetime of the end product. For this type of requirement a low cost consumer grade Flash card would just not suffice.

Fortasa Memory Systems, Inc. manufactures Industrial Grade SD card specifically for the OEM and Industrial customers. Utilizing high reliability SLC NAND Flash or cost effective MLC NAND Flash, Fortasa’s SD Cards offer the highest degree of quality and reliability. These devices go through a significant production qualification tests verifying consistent and reliable operation at voltage and temperature corners, under extreme shock and vibration and even under power supply brown-out conditions.

Please contact Fortasa about our Industrial SD Card Products Information and Reliability Report.

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This is a continuation of the discussion of Flash SSD Power Failure Corruption Prevention, Recovery and Test 

File System Basics

To assess the inherent vulnerability of the specific storage system to the power disruptions it’s important to understand the typical Operating Systems file structure:

Operating System File Structure

The Address space of the storage system consists of the following:

Category Description

1.     Drive Firmware

Flash Controller code for internal operation

2.     Identify Drive

Drive Specific configuration information to be read by the host at the initialization stage to recognize the features and capabilities of the drive

3.     Master Boot Record (MBR)

Drive specific record that contains partition and boot information that the system reads and interprets to address the drive

4.     File Allocation Table (FAT)

A Operating System table that links discrete address locations into sequential file structure. Due to drive efficiency or fragmentation, pages can be scattered across the whole drive address space and FAT table keeps track of the sequential data locations to recreate the stored file.

5.     Operating System

Critical files to enable host system operation and execution of required programs. These files are Operating Systems unique.

6.     User Data

Files that are most frequently updated, erased or modified.

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This is a continuation of the discussion of Flash SSD Power Failure Corruption Prevention, Recovery and Test 

Data Corruption Mechanism

During the typical drive operation, data is accessed by the host through either a read or write command to the memory system. The write command for Flash memory actually consists of two separate actions, an erase and subsequent program.

If a power disruption occurs during a read command, then there is no direct disturbance to the stored information, except for the unlikely occurrence of the Read disturb phenomenon, and the host system can typically re-execute the last command without any issues after a system reset and recovery routine.

Memory Corruption

Flash Data Corruption

In the second case, If the power disturbance occurs during an erase command execution, the block being erased might not get erased fully, and during the subsequent program of this block would exhibit a program error forcing the host to reissue the same program command to a different address location. Aside from a repeat command execution, a power disturbance during an erase command would not harm the solid state drive. A side note that in the erase command scenario, while the data corruption will not affect any useful data, the corrupted block will most likely be retired as a bad block after a subsequent program failure will occur with this memory block.

In the third case, if a power glitch occurs during a program command the consequences can be quite severe. And depending whether the program command was for the user data, FAT table or Master Boot Record, the effects of the corruption could be quite severe.

Please contact Fortasa for any information about power failure prevention of our Flash storage products.

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Flash Controller Basics

To overcome the vulnerability of Flash memory to power glitches, memory system designers have utilized advanced memory management techniques. The most frequently used technique involves usage of Error Correction Code (ECC) to detect the failure and correct the data. The ECC algorithm calculates special code based on the user data and programs this code in the overhead space for each programmed page. When the data is read, the ECC algorithm verifies it against the calculated value. In case of discrepancy, the ECC algorithm can correct the read data (within certain statistical limitation) based on the stored special code. Depending on product specification, Fortasa Memory Systems solutions offer ECC correction capability substantially greater than is recommended by the Flash memory suppliers. This “safety measure” can correct upto 99% of data corruptions in a typical application.

The single bit errors in a programmed page can occur due to a number of unrelated factors. The most common of which are:
1) Bad Flash Media – After a great number of program erase cycles the Flash memory cells degrades to the point where a programmed level (1 or 0) can’t be easily determined by the Flash controller.
2) Read Disturb - Read Disturb phenomenon (more prominently exhibited in the MLC NAND Flash) – is an affect that reading data from one Flash cell has on an adjacent Flash cell. The power applied to read the state of one memory cell actually affects the charge of an adjacent cell to the point to the point where a programmed level (1 or 0) can’t be easily determined by the Flash controller.
3) Program Disturb - Program Disturb phenomenon more prominently exhibited in the MLC NAND Flash) – is an affect that programming data from one Flash cell has on an adjacent Flash cell. The power applied to change the state of one memory cell actually affects the charge of an adjacent cell to the point to the point where a programmed level (1 or 0) can’t be easily determined by the Flash controller.

While the ECC algorithm is powerful enough to overcome all aforementioned single bit errors, in a small number of cases the number of affected bits within a programed page is so large, that is not able to be corrected by an ECC algorithm. This case is called an uncorrectable read failure and if not considered properly during the electronic system design, can have grave consequences.

Please contact Fortasa for any information about power failure prevention of our Flash storage products.

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Flash Memory Basics

NAND Flash memory is the base storage medium of the Solid State Drives. A Flash memory cell works on the principle that there is a distinguishable stored charge inside the cell which corresponds to either a programmed or erased condition. A peripheral circuitry can check the status of the cell (read) and determine which state the cell is in. The greater the difference between the erased and programmed condition the easier it’s to distinguish the cell state.

During a Flash program operation, the logic circuit pumps electrical charge into the memory cell raising  the charge level to a distinguishable condition corresponding to one. During the erase operation, the charge is removed from the memory cell to the level corresponding to zero.
However, if a power disruption occurs during the cell charge or discharge operation, the cell could be left in an opposite or even more dangerously indistinguishable state. What makes this single cell failure truly catastrophic is the fact that NAND Flash memory architecture allows, multiple cells, called page, to be programmed concurrently. While this architectural advancement increases the programming throughput, it creates gross vulnerability for data integrity in case of power disruption.

MLC NAND Flash Architecture

MLC NAND Flash Architecture

 

The issue of power disruption during cell program or erase operation is exacerbated when using Multi Level Cell Flash (MLC) memory. The physical architecture of MLC Flash is that two different pages which could be non-contiguous (separated) share the same memory cell. As an illustration, if a program operation on page A in an MLC device is interrupted another page B could also be affected by the program interruption. The relative location of the paired page B may vary in the same device and also from manufacturer to manufacturer.

Please contact Fortasa for any information about power failure prevention of our Flash storage products.

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