Flash Storage Solutions for Embedded Designs
High Reliability Flash SSDs, Cards and Modules for Industrial Applications
Posted by John Kuracek on Tuesday, 27 May 2014
This is a continuation of the discussion of Flash SSD Power Failure Corruption Prevention, Recovery and Test
Flash Controller Basics
To overcome the vulnerability of Flash memory to power glitches, memory system designers have utilized advanced memory management techniques. The most frequently used technique involves usage of Error Correction Code (ECC) to detect the failure and correct the data. The ECC algorithm calculates special code based on the user data and programs this code in the overhead space for each programmed page. When the data is read, the ECC algorithm verifies it against the calculated value. In case of discrepancy, the ECC algorithm can correct the read data (within certain statistical limitation) based on the stored special code. Depending on product specification, Fortasa Memory Systems solutions offer ECC correction capability substantially greater than is recommended by the Flash memory suppliers. This “safety measure” can correct upto 99% of data corruptions in a typical application.
The single bit errors in a programmed page can occur due to a number of unrelated factors. The most common of which are:
1) Bad Flash Media - After a great number of program erase cycles the Flash memory cells degrades to the point where a programmed level (1 or 0) can't be easily determined by the Flash controller.
2) Read Disturb - Read Disturb phenomenon (more prominently exhibited in the MLC NAND Flash) - is an affect that reading data from one Flash cell has on an adjacent Flash cell. The power applied to read the state of one memory cell actually affects the charge of an adjacent cell to the point to the point where a programmed level (1 or 0) can't be easily determined by the Flash controller.
3) Program Disturb - Program Disturb phenomenon more prominently exhibited in the MLC NAND Flash) - is an affect that programming data from one Flash cell has on an adjacent Flash cell. The power applied to change the state of one memory cell actually affects the charge of an adjacent cell to the point to the point where a programmed level (1 or 0) can't be easily determined by the Flash controller.
While the ECC algorithm is powerful enough to overcome all aforementioned single bit errors, in a small number of cases the number of affected bits within a programed page is so large, that is not able to be corrected by an ECC algorithm. This case is called an uncorrectable read failure and if not considered properly during the electronic system design, can have grave consequences.
Please contact Fortasa for any information about power failure prevention of our Flash storage products.